In conventional integrated multiplication circuits, a two-dimensional M.times.N array of multiplying stages is used for multiplication of a multiplier of N bits with a multiplicand of M bits. This requires a large number of multiplying stages, which increases geometrically with the number of bits in the multiplier and multiplicand. Moreover, the multiplying stages are operated on a system clock signal, which is inefficient in that the multiplying stages usually can operate at processing speeds faster than the system clock signal.